Many systems and architectures require the communication of high bandwidth information between a mainstream technology-based analog front-end, containing an analog-to-digital (AD) converter, and a high end technology based System-On-Chip (SOC). Previous implementations either solved this problem through the use of a slow parallel bus interface or have applied a different architecture in which the AD conversion is implemented on the SOC.
Parallel bus implementations become physically unmanageable and expensive for high bandwidths. Typically, such a wide bus must be implemented with single ended signaling, which is critical for Electromagnetic Emission (EME) in an application where the analog front-end is sensitive.
When AD conversion is implemented on the SOC, the increasing use of lower supply voltages and deeper submicron technologies make the use and design of implementable AD converters very challenging, and it is difficult for the analog design to keep up with fast shrinking technologies used for SOC development.